FIG. 3 sets forth a conventional semiconductor memory. The semiconductor memory arrangement of FIG. 3 can be referred to as a virtual channel memory. The virtual channel memory is designated by the general reference character 300 and can include a number of dynamic random access memory (DRAM) cells arranged into a memory cell array 302. Memory cell array 302 can include DRAM cells arranged in row and column directions.
The virtual channel memory 300 can also include a register array section 304. A register array section 304 can include a number of registers arranged in row and column directions. The number of rows and/or columns can be a predetermined ratio of the number of rows and columns in the memory cell array 302. A register array section 304 can have a "cache" function.
One skilled in the art would recognize that a cache can store a portion of the data stored in a memory cell array. Access to the cache can be faster than access to the memory cell array. Data read operations can access a cache. If the data is stored within, there is a cache "hit" and the data can be accessed from a register array section 304. If the data is not stored within the cache there is a cache "miss."
The memory cell array 302 and register array section 304 can be connected to each other by transfer buses TBT1-1 to TBN1-i. Additional transfer buses TBT2-1 to TBN2-i can be connected to the register array section 304. A read/write bus RWBT and RWBN can be connected to transfer buses TBT1-1 to TBN1-i and TBT2-1 to TBN2-i.
Data values of the conventional virtual RAM of FIG. 3 can be read in a number of different ways. One type of read operation is a "continuous" read operation. One skilled in the art would recognize that a continuous read operation can be a series of read operations that occur one after another. As just one example, a continuous read operation may include a number of read operations that access the same row address, but different column addresses. A continuous read operation can include a "miss" to the register array section 304. In a conventional continuous read operation that results in a register array miss, read data from memory cell array 302 is temporarily transferred to register array section 304 by way of transfer buses TBT1-1 to TBN1-i. The data may then be read from the register array section 304 by way of transfer buses TBT2-1 to TBN2-i.
In another type of read operation, data may be read directly from the memory cell array 302, and not through register array section 304. In such a read operation, data may be read by way of transfer buses TBT1-1 to TBN1-i to local read/write bus LRWBT and LRWBN.
Data values may also be written to the virtual channel memory 300 in different ways. Data within register array section 304 may be written into memory cell array 302 by way of transfer buses TBT1-1 to TBN1-i. Data may also be written to memory cell array 302 without using register array section 304. Data on a local read/write bus LRWBT and LRWBN may be written into memory cell array 302 by way of transfer buses TBT1-1 to TBN1-i.
The above-described approach to a virtual channel memory can have drawbacks. In the case of a continuous read operation, resulting from a register miss, data read from memory cell array 302 is temporarily transferred to register array section 304, and then read afterward from the register array section 304. As a result, continuous read operations may take considerable time.